DK-DEV-5SGXEA7N【PDF 21/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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LAB Power Management Techniques

SV51002

2014.01.10

an LAB while leaving the other half available for narrower fan-in functionality. In every LAB, the column

is top-half bypassable; while in MLAB, columns are bottom-half bypassable.

The Quartus II Compiler creates shared arithmetic chains longer than 20 ALMs (10 ALMs in arithmetic or

shared arithmetic mode) by linking LABs together automatically. To enhance fitting, a long shared arithmetic

chain runs vertically, allowing fast horizontal connections to the TriMatrix memory and DSP blocks. A

shared arithmetic chain can continue as far as a full column.

LAB Power Management Techniques

The following techniques are used to manage static and dynamic power consumption within the LAB:

? To save AC power, the Quartus II software forces all adder inputs low when the ALM adders are not in

use.

? Stratix V LABs operate in high-performance mode or low-power mode. The Quartus II software

automatically chooses the appropriate mode for the LAB, based on your design and to optimize speed

versus leakage trade-offs.

? Clocks represent a significant portion of dynamic power consumption because of their high switching

activity and long paths. The LAB clock that distributes a clock signal to registers within a LAB is a

significant contributor to overall clock power consumption. Each LAB ’ s clock and clock enable signals

are linked. For example, a combinational ALUT or register in a particular LAB using the labclk1 signal

also uses the labclkena1 signal. To disable a LAB-wide clock power consumption without disabling the

entire clock tree, use the LAB-wide clock enable to gate the LAB-wide clock. The Quartus II software

automatically promotes register-level clock enable signals to the LAB-level. All registers within the LAB

that share a common clock and clock enable are controlled by a shared, gated clock. To take advantage

of these clock enables, use a clock-enable construct in your HDL code for the registered logic.

Related Information

Power Optimization chapter, Quartus II Handbook

Provides more information about implementing static and dynamic power consumption within the LAB.

Document Revision History

Date

January 2014

Altera Corporation

Version

2014.01.10

Changes

Added multiplexers for the bypass paths and register outputs in the

following diagrams:

? ALM High-Level Block Diagram for Stratix V Devices

? Input Function in Normal Mode

? Template for Supported 7-Input Functions in Extended LUT Mode for

Stratix V Devices

? ALM in Arithmetic Mode for Stratix V Devices

? ALM in Shared Arithmetic Mode for Stratix V Devices

Logic Array Blocks and Adaptive Logic Modules in Stratix V Devices

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